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EP1C6Q240C8N MCU Microcontroller Unit 92160 Total RAM Bits Active Part Status

China EP1C6Q240C8N MCU Microcontroller Unit 92160 Total RAM Bits Active Part Status supplier

Large Image :  EP1C6Q240C8N MCU Microcontroller Unit 92160 Total RAM Bits Active Part Status

Product Details:

Place of Origin: Original
Brand Name: Original Manufacturer
Certification: Rosh
Model Number: EP1C6Q240C8N

Payment & Shipping Terms:

Minimum Order Quantity: 1
Price: Negotiation
Packaging Details: Original Packing
Delivery Time: In stock
Payment Terms: TT, Paypal, Western Union And So On
Supply Ability: 80000
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Detailed Product Description
Part Status: Active Number Of LABs/CLBs: 598
Number Of Logic Elements/Cells: 5980 Total RAM Bits: 92160
Number Of I/O: 185 Voltage - Supply: 1.425 V ~ 1.575 V
Mounting Type: Surface Mount Operating Temperature: 0°C ~ 85°C (TJ)

 

EP1C6Q240C8N MCU Microcontroller Unit IC FPGA 185 I/O 240QFP

 

Part Status Active  
Number of LABs/CLBs 598  
Number of Logic Elements/Cells 5980  
Total RAM Bits 92160  
Number of I/O 185  
Voltage - Supply 1.425 V ~ 1.575 V  
Mounting Type Surface Mount  
Operating Temperature 0°C ~ 85°C (TJ)  
Package / Case 240-BFQFP  
Supplier Device Package 240-PQFP (32x32)  
Base Part Number EP1C6

 

Introduction The Cyclone® field programmable gate array family is based on a 1.5-V, 0.13-mm, all-layer copper SRAM process, with densities up to

20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.

 

Features The Cyclone device family offers the following features:

■ 2,910 to 20,060 LEs, see Table 1–1

■ Up to 294,912 RAM bits (36,864 bytes)

■ Supports configuration through low-cost serial configuration device

■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard

■ High-speed (640 Mbps) LVDS I/O support

■ Low-speed (311 Mbps) LVDS I/O support

■ 311-Mbps RSDS I/O support

■ Up to two PLLs per device provide clock multiplication and phase shifting

■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row

■ Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM

■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

 

Table 1–1. Cyclone Device Features (Part 1 of 2)
Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
LEs 2,910 4,000 5,980 12,060 20,060
M4K RAM blocks (128 ´ 36 bits) 13 17 20 52 64

 

 

 
  EP1C6Q240C8N MCU Microcontroller Unit 92160 Total RAM Bits Active Part Status

Cyclone Device Handbook, Volume 1

 

 

 

Table 1–1. Cyclone Device Features (Part 2 of 2)
Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20
Total RAM bits 59,904 78,336 92,160 239,616 294,912
PLLs 1 2 2 2 2
Maximum user I/O pins (1) 104 301 185 249 301

Note to Table 1–1:

(1) This parameter includes global clock pins.

 

Cyclone devices are available in quad flat pack (QFP) and space-saving FineLine® BGA packages (see Tables 1–2 through 1–3).

 

Table 1–2. Cyclone Package Options and I/O Pin Counts
Device

100-Pin TQFP

(1)

144-Pin TQFP

(1), (2)

240-Pin PQFP

(1)

256-Pin

FineLine BGA

324-Pin

FineLine BGA

400-Pin

FineLine BGA

EP1C3 65 104
EP1C4 249 301
EP1C6 98 185 185
EP1C12 173 185 249
EP1C20 233 301

Notes to Table 1–2:

(1) TQFP: thin quad flat pack. PQFP: plastic quad flat pack.

(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).

 

Vertical migration means you can migrate a design from one device to another that has the same dedicated pins, JTAG pins, and power pins, and are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must use the layout for the largest planned density in a package to provide the necessary power pins for migration.

 

For I/O pin migration across densities, cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus® II software can automatically cross-reference and place all pins for you when given a device migration list. If one device has power or ground pins, but these same pins are user I/O on a different device that is in the migration path,the Quartus II software ensures the pins are not used as user I/O in the Quartus II software. Ensure that these pins are connected

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MDM9225M-1VV BGA QUALCOMM 1812
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MDM9615 BGA QUALCOMM 524
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ME1101026B BGA POLARIS 168000
MFM60A0 BGA GF-MH 1099
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MN103SE00 BGA Panasonic 1
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