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DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J

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DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J

China DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J supplier

Large Image :  DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J

Product Details:

Place of Origin: Original
Brand Name: Original Manufacturer
Certification: RoHS
Model Number: MT41K64M16TW-107:J

Payment & Shipping Terms:

Minimum Order Quantity: 1
Price: Negotiation
Packaging Details: Original Packing
Delivery Time: In stock
Payment Terms: TT, Paypal, Western Union And So On
Supply Ability: 80000
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Detailed Product Description
DRAM Type: DDR3L SDRAM Chip Density (bit): 1G
Organization: 64Mx16 Number Of Internal Banks: 8
Number Of Bits/Word (bit): 16 Maximum Clock Rate (mhz): 933

MT41K64M16TW-107:J DRAM Chip DDR3L SDRAM 1Gbit 64Mx16 1.35V 96-Pin FBGA

 

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.

Key Features

  • VDD = VDDQ = +1.35V (1.283V to 1.45V)
  • Backward compatible to VDD = VDDQ = 1.5V ±0.075V
  • Differential bidirectional data strobe
  • 8n-bit prefetch architecture
  • Differential clock inputs (CK, CK#)
  • 8 internal banks
  • Nominal and dynamic on-die termination (ODT)for data, strobe, and mask signals
  • Programmable CAS (READ) latency (CL)
  • Programmable CAS additive latency (AL)
  • Programmable CAS (WRITE) latency (CWL)
  • Fixed burst length (BL) of 8 and burst chop (BC) of 4(via the mode register set [MRS])
  • Selectable BC4 or BL8 on-the-fly (OTF)
  • Self refresh mode
  • TC of 0°C to 95°C
  • 64ms, 8192-cycle refresh at 0°C to 85°C
  • 32ms at 85°C to 95°C
  • Self refresh temperature (SRT)
  • Automatic self refresh (ASR)
  • Write leveling
  • Multipurpose register
  • Output driver calibration

Technical Attributes

Description
Value
Find similar Parts
Product Dimensions
8 x 14 x 0.965
 
Operating Temperature
0 to 95 °C
 
Number of I/O Lines
16 Bit
 
Number of Bits per Word
16 Bit
 
Density
1 Gb
 
Type
DDR3L SDRAM
 
Address Bus Width
13 Bit
 
Data Bus Width
16 Bit
 
Screening Level
Commercial
 
Max Processing Temp
260
 
Lead Finish
Tin|Silver|Copper
 
Maximum Clock Rate
933 MHz
 
Pin Count
96
 
Operating Supply Voltage
1.35 V
 
Organization
64M x 16
 
Supplier Package
FBGA
 
Maximum Operating Current
63 mA
 
Mounting
Surface Mount
 
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ECCN / UNSPSC

 

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542320023
HTSN:
8542320022
UNSPSC:
32101602
UNSPSC VERSION:
V15.1101
DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J
DDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:JDDR3L SDRAM Memory IC Chip 16 Bits 8 Internal Banks MT41K64M16TW-107:J

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Contact Person: Cary

Tel: +8613760106370

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